View NCV7356D1_7949522.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

? semiconductor components industries, llc, 2005 january, 2005 ? rev. p5 1 publication order number: ncv7356/d ncv7356 advance information single wire can transceiver the ncv7356 is a physical layer device for a single wire data link capable of operating with various carrier sense multiple access with collision resolution (csma/cr) protocols such as the bosch controller area network (can) version 2.0. this serial data link network is intended for use in applications where high data rate is not required and a lower data rate can achieve cost reductions in both the physical media components and in the microprocessor and/or dedicated logic devices which use the network. the network shall be able to operate in either the normal data rate mode or a high?speed data download mode for assembly line and service data transfer operations. the high?speed mode is only intended to be operational when the bus is attached to an off?board service node. this node shall provide temporary bus electrical loads which facilitate higher speed operation. such temporary loads should be removed when not performing download operations. the bit rate for normal communications is typically 33 kbit/s, for high?speed transmissions like described above a typical bit rate of 83 kbit/s is recommended. the ncv7356 is designed in accordance to the single wire can physical layer specification gmw3089 v2.3 and supports many additional features like undervoltage lockout, timeout for faulty blocked input signals, output blanking time in case of bus ringing and a very low sleep mode current. features ? fully compatible with j2411 single wire can specification ? 60 a (max) sleep mode current ? operating voltage range 5.0 to 27 v ? up to 100 kbps high?speed transmission mode ? up to 40 kbps bus speed ? selective bus wake?up ? logic inputs compatible with 3.3 v and 5 v supply systems ? control pin for external voltage regulators (14 pin package only) ? standby to sleep mode timeout ? low rfi due to output wave shaping ? fully integrated receiver filter ? bus terminals short?circuit and transient proof ? loss of ground protection ? protection against load dump, jump start ? thermal overload and short circuit protection ? esd protection of 4.0 kv on can pin (2.0 kv on any other pin) ? undervoltage lock out ? bus dominant timeout feature ? ncv prefix for automotive and other applications requiring site and change control this document contains information on a new product. specifications and information herein are subject to change without notice. so?14 d suffix case 751a 1 14 pin connections device package shipping 2 ordering information NCV7356D1 soic?8 98 units / rail http://onsemi.com marking diagrams ncv7356 awlyww 1 14 14 (top view) txd mode1 nc canh mode0 rxd v bat load 1 13 2 12 3 11 4 10 5 9 6 8 7 gnd gnd nc inh gnd gnd NCV7356D1r2 soic?8 2500 tape & reel 2for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specification brochure, brd8011/d. ncv7356d2 soic?14 55 units / rail ncv7356d2r2 soic?14 1000 tape & reel so?8 d suffix case 751 1 8 v7356 alyw 1 8 a = assembly location wl, l = wafer lot yy, y = year ww, w = work week 1 txd 8 gnd 2 mode0 3 mode1 4 rxd 7 canh 6 load 5v bat (top view)
ncv7356 http://onsemi.com 2 figure 1. 8?pin package block diagram v bat ncv7356 5 v supply and references biasing and v bat monitor rc?osc wave shaping time out txd mode control mode0 mode1 rxd reverse current protection can driver feedback loop input filter receive comparator loss of ground detection canh load gnd reverse current protection rxd blanking time filter
ncv7356 http://onsemi.com 3 figure 2. 14?pin package block diagram v bat ncv7356 5 v supply and references biasing and v bat monitor rc?osc wave shaping time out txd mode control mode0 mode1 rxd reverse current protection can driver feedback loop input filter receive comparator loss of ground detection canh load gnd reverse current protection rxd blanking time filter inh
ncv7356 http://onsemi.com 4 package pin description soic?8 soic?14 symbol description 1 2 txd transmit data from microprocessor to can. 2 3 mode0 operating mode select input 0. 3 4 mode1 operating mode select input 1. 4 5 rxd receive data from can to microprocessor. 5 10 v bat battery input voltage. 6 11 load resistor load (loss of ground detection low side switch). 7 12 canh single wire can bus pin. 8 1, 7, 8, 14 gnd ground ? 6, 13 nc no connection ? 9 inh control pin for external voltage regulator (high voltage high side switch) (14 pin package only)
ncv7356 http://onsemi.com 5 electrical specification all voltages are referenced to ground (gnd). positive currents flow into the ic. the maximum ratings given in the table below are limiting values that do not lead to a permanent damage of the device but exceeding any of these limits may do so. long term exposure to limiting values may affect the reliability of the device. maximum ratings rating symbol condition min max unit supply v oltage, normal operation v bat ? ?0.3 18 v short?term supply v oltage, t ransient v bat.ld load dump; t < 500 ms ? 40 v (peak) jump start; t < 1.0 min ? 27 v transient supply voltage v bat.tr1 iso 7637/1 pulse 1 (note 1) ?50 ? v transient supply voltage v bat.tr2 iso 7637/1 pulses 2 (note 1) ? 100 v transient supply voltage v bat.tr3 iso 7637/1 pulses 3a, 3b ?200 200 v canh voltage v canh v bat < 27 v ?20 40 v v bat = 0 v ?40 40 transient bus voltage v canhtr1 iso 7637/1 pulse 1 (note 2) ?50 ? v transient bus voltage v canhtr2 iso 7637/1 pulses 2 (note 2) ? 100 v transient bus voltage v canhtr3 iso 7637/1 pulses 3a, 3b (note 2) ?200 200 v dc voltage on pin load v load via rt > 2.0 k ?40 40 v dc voltage on pins txd, mode1, mode0, rxd v dc ? ?0.3 7.0 v esd capability of canh v esdbus human body model eq. to discharge 100 pf with 1.5 k ?4000 4000 v esd capability of any other pins v esd human body model eq. to discharge 100 pf with 1.5 k ?2000 2000 v maximum latch?up free current at any pin i latch ? ?500 500 ma maximum power dissipation, 8 pin package p tot at t a = 125 c ? tbd (note 3) mw thermal impedance, 8 pin package ja in free air ? tbd c/w maximum power dissipation, 14 pin package p tot at t a = 125 c ? >400 (note 3) mw thermal impedance, 14 pin package ja in free air ? <70 c/w storage t emperature t stg ? ?55 150 c junction temperature t j ? ?40 150 c lead temperature soldering reflow: (smd styles only) t sld 60 second maximum above 183 c ?5 c/+0 c allowable conditions ? 240 peak c maximum ratings are those values beyond which device damage can occur. maximum ratings applied to the device are individual stress limi t values (not normal operating conditions) and are not valid simultaneously. if these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. 1. iso 7637 test pulses are applied to v bat via a reverse polarity diode and >1.0 f blocking capacitor. 2. iso 7637 test pulses are applied to canh via a coupling capacitance of 1.0 nf. 3. the application board shall be realized with a ground copper foil area > 150 mm 2 .
ncv7356 http://onsemi.com 6 electrical characteristics (v bat = 5.0 to 27 v, t a = ?40 to +125 c, unless otherwise specified.) characteristic symbol condition min typ max unit general undervoltage lock out v batuv ? 4.0 ? 4.8 v supply current, recessive, all active modes i batn v bat = 18 v, txd open ? 5.0 8.0 ma normal mode supply current, dominant i batn (note 4) v bat = 27 v, mode0 = mode1 = h, txd = l, r load = 200 ? 30 35 ma high?speed mode supply current, dominant i batn (note 4) v bat = 16 v, mode0 = h, mode1 = l, txd = l, r load = 75 ? 70 75 ma wake?up mode supply current, dominant i batw (note 4) v bat = 27 v, mode0 = l, mode1 = h, txd = l, r load = 200 ? 60 75 ma sleep mode supply current i bats v bat = 18 v, txd, rxd, mode0, mode1 open ? 30 60 a thermal shutdown (note 4) t sd ? 155 ? 180 c thermal recovery (note 4) t rec ? 126 ? 150 c canh bus output voltage v oh r l > 200 , normal mode 6.0 v < v bat < 27 v 4.4 ? 5.1 v bus output voltage low battery v oh r l > 200 , normal high?speed mode 5.0 v < v bat < 6.0 v 3.4 ? 5.1 v bus output voltage high?speed mode v oh r l > 75 , high?speed mode 8.0 v < v bat < 16 v 4.2 ? 5.1 v fixed wake?up output high voltage v ohwufix wake?up mode, r l > 200 , 11.4 v < v bat < 27 v 9.9 ? 12.5 v offset wake?up output high voltage v ohwuoffset wake?up mode, r l > 200 , 5.0 v < v bat < 11.4 v v bat 1.5 ? v bat v recessive state output voltage v ol recessive state or sleep mode, r load = 6.5 k ?0.20 ? 0.20 v bus short circuit current ?i can_short v canh = 0 v, v bat = 27 v, txd = 0 v 50 ? 350 ma bus leakage current during loss of ground i lkn_can (note 5) loss of ground, v canh = 0 v ?50 ? 10 a bus leakage current, bus positive i lkp_can txd high ?10 ? 10 a bus input threshold v ih normal, high?speed mode, 6.0 v bat 27 v 2.0 2.1 2.2 v bus input threshold low battery v ihlb normal, v bat = 5.0 v 1.6 1.7 1.8 v fixed wake?up input high voltage threshold v ihwufix (note 4) sleep mode, v bat > 10.9 v 6.6 ? 7.9 v offset wake?up input high voltage threshold v ihwuoffset (note 4) sleep mode v bat ?4.3 ? v bat ?3.25 v load voltage on switched ground pin v load_1ma i load = 1.0 ma ? ? 0.1 v voltage on switched ground pin v load i load = 5.0 ma ? ? 0.5 v voltage on switched ground pin v load_lob i load = 7.0 ma, v bat = 0 v ? ? 1.0 v load resistance during loss of battery r load_lob v bat = 0 r load ?10% ? r load +35% 4. thresholds not tested in production, guaranteed by design. 5. leakage current in case of loss of ground is the summary of both currents i lkn_can and i lkn_load .
ncv7356 http://onsemi.com 7 electrical characteristics (continued) (v bat = 5.0 to 27 v, t a = ?40 to +125 c, unless otherwise specified.) characteristic symbol condition min typ max unit txd, mode0, mode1 high level input v oltage v ih 5.0 < v bat < 27 v 2.0 ? ? v low level input v oltage v il 5.0 < v bat < 27 v ? ? 0.8 v txd pull up current ?i il_txd txd = l, mode0 and 1 = h 5.0 < v bat < 27 v 15 ? 50 a mode0 and 1 pull down resistor r mode_pd 20 ? 50 k rxd low level output voltage v ol_rxd i rxd = 2.0 ma ? ? 0.4 v high level output leakage i ih_rxd v rxd = 5.0 v ?10 ? 10 a rxd output current irxd v rxd = 5.0 v ? ? 70 ma inh (14 pin package only) high level output voltage v oh_inh i inh = ?180 a v bat ?0.8 v bat ?0.5 ? v leakage current i inh_lk mode0 = mode1 = l, inh = 0 v ?5.0 ? 5.0 a
ncv7356 http://onsemi.com 8 timing measurement load conditions normal and high v oltage wake?up mode high?speed mode min load / min tau 3.3 kohm / 540 pf additional 140 ohm tool resistance to ground in parallel min load / max tau 3.3 kohm / 1.2 nf to ground in parallel max load / min tau 200 ohm / 5.0 nf additional 120 ohm tool resistance to ground in parallel max load / max tau 200 ohm / 20 nf to ground in parallel electrical characteristics (5.0 v v bat 27 v, ?40 c t a 125 c, unless otherwise specified.) ac characteristics (see figures 3, 4, and 5) characteristic symbol condition min typ max unit transmit delay in normal and w ake?up mode, bus rising edge (note 6) t tr min and max loads per t iming measurement load conditions 2.0 ? 6.3 s transmit delay in wake?up mode to v ihwu , bus rising edge (note 7) t twur min and max loads per t iming measurement load conditions 2.0 ? 18 s transmit delay in normal mode, bus falling edge (note 8) t tf min and max loads per t iming measurement load conditions 1.8 ? 10 s transmit delay in wake?up mode, bus falling edge (note 8) t twu1f min and max loads per t iming measurement load conditions 3.0 ? 13.7 s transmit delay in high?speed mode, bus rising edge (note 9) t thsr min and max loads per t iming measurement load conditions 0.1 ? 1.5 s transmit delay in high?speed mode, bus falling edge (note 10) t thsf min and max loads per t iming measurement load conditions 0.1 ? 3.0 s receive delay, all active modes (note 11) t dr canh high to low transition 0.3 ? 1.0 s receive delay, all active modes (note 11) t rd canh low to high transition 0.3 ? 1.0 s input minimum pulse length, all active modes (note 11) t mpdr t mprd canh high to low transition canh low to high transition 0.15 0.15 ? ? 1.0 1.0 s wake?up filter time delay t wuf see figure 4 10 ? 70 s receive blanking time after txd l?h transition t rb see figure 5 0.5 ? 6.0 s txd timeout reaction time t tout normal and high?speed mode ? 20 ? ms txd timeout reaction time t toutwu wake?up mode ? 30 ? ms delay from normal to high?speed and high voltage wake?up mode t dnhs ? ? ? 30 s delay from high?speed and high voltage wake?up to normal mode t dhsn ? ? ? 30 s delay from normal to standby mode t dsby v bat = 6.0 v to 27 v ? ? 500 s delay from sleep to normal mode t dsnwu v bat = 6.0 v to 27 v ? ? 50 s delay from standby to sleep mode (note 12) t dsleep v bat = 6.0 v to 27 v 100 250 1000 ms 6. the maximum signal delay time for a bus rising edge is measured from v cmos_il on the txd input pin to the v ihmax + v goff max level on canh at maximum network time constant, minimum signal delay time for a bus rising edge is measured from v cmos_ih on the txd input pin to 1 v on canh at minimum network time constant. these definitions are valid in both normal and high voltage wake?up (hvwu) mode. 7. the maximum signal delay time for a bus rising edge in hvwu mode is measured from v cmos_il on the txd input pin to the v ihwumax + v goff max level on canh at maximum network time constant, minimum signal delay time for a bus rising edge is measured from v cmos_ih on the txd input pin to 1 v on canh at minimum network time constant. 8. maximum signal delay time for a bus falling edge is measured from v cmos_ih on the txd input pin to 1 v on canh at maximum network time constant, minimum signal delay time for a bus falling edge is measured from v cmos_ih on the txd input pin to the v ihmax + v goff max level on canh. these definitions are valid in both normal and hvwu mode. 9. the signal delay time in high?speed mode for a bus rising edge is measured from v cmos_il on the txd input pin to the v ihmax + v goff max level on canh at maximum high?speed network time constant. 10. the signal delay time in high?speed mode for a bus falling edge is measured from v cmos_ih on the txd input pin to 1 v on canh at maximum high?speed network time constant. 11. receive delay time is measured from the rising / falling edge crossing of the nominal v ih value on canh to the falling (v cmos_il_max ) / rising (v cmos_ih_min ) edge of rxd. this parameter is tested by applying a square wave signal to canh. the minimum slew rate for the bus rising and falling edges is 50 v/ s. the low level on bus is always 0v. for normal mode and high?speed mode testing the high level on bus is 4 v. for hvwu mode testing the high level on bus is v bat ? 2 v. 12. tested on 14 pin package only.
ncv7356 http://onsemi.com 9 bus loading requirements characteristic symbol min typ max unit number of system nodes ? 2 ? 32 ? network distance between any two ecu nodes bus length ? ? 60 m node series inductor resistance (if required) r ind ? ? 6.0 ground offset voltage v goff ? ? 1.5 v ground offset voltage, low battery v gofflowbat ? 0.1 x v bat 0.7 v device capacitance (unit load) c ul 198 220 300 pf network total capacitance c tl 396 ? 19000 pf device resistance (unit load) r ul 6435 6490 6565 device resistance (min load) r min 2000 ? ? network total resistance r tl 200 ? 4596 network time constant (note 13) 1.0 ? 4.0 s network time constant in high?speed mode ? ? 1.5 s high?speed mode network resistance to gnd r load 75 ? 135 13. the network time constant incorporates the bus wiring capacitance. the minimum value is selected to limit radiated emission. the maximum value is selected to ensure proper communication modes. not all combinations of r and c are possible. timing diagrams figure 3. input/output timing v ih max + v goff max t t v canh v rxd 1 v 50% v txd 50% t t t t r t f t d t dr
ncv7356 http://onsemi.com 10 timing diagrams figure 4. wake?up filter time delay v canh v rxd t t t wu t wuf t wu t wu < t wuf v ih + v goff wake?up interrupt figure 5. receive blanking time v ih v canh v rxd 50% v txd 50% t t t t rb
ncv7356 http://onsemi.com 11 functional description txd input pin txd polarity ? txd = logic 1 (or floating) on this pin produces an undriven or recessive bus state (low bus voltage) ? txd = logic 0 on this pin produces either a bus normal or a bus high voltage dominant state depending on the transceiver mode state (high bus voltage) if the txd pin is driven to a logic low state while the sleep mode (mode 0 = 0 and mode 1 = 0) is activated, the transceiver can not drive the canh pin to the dominant state. the transceiver provides an internal pull up current on the txd pin which will cause the transmitter to default to the bus recessive state when txd is not driven. txd input signals are standard cmos logic levels. timeout feature in case of a faulty blocked dominant txd input signal, the canh output is switched off automatically after the specified txd timeout reaction time to prevent a dominant bus. the transmission is continued by next txd l to h transition without delay. mode0 and mode1 pins the transceiver provides a weak internal pull down current on each of these pins which causes the transceiver to default to sleep mode when they are not driven. the mode input signals are standard cmos logic level for 3.3v and 5v supply voltages. mode0 mode1 mode l l sleep mode h l high?speed mode l h high voltage w ake?up h h normal mode sleep mode transceiver is in low power state, waiting for wake?up via high voltage signal or by mode pins change to any state other than 0,0. in this state, the canh pin is not in the dominant state regardless of the state of the txd pin. high?speed mode this mode allows high?speed download with bitrates up to 100 kbit/s. the output waveshaping circuit is disabled in this mode. bus transmitter drive circuits for those nodes which are required to communicate in high?speed mode are able to drive reduced bus resistance in this mode. high voltage wake?up mode this bus includes a selective node awake capability, which allows normal communication to take place among some nodes while leaving the other nodes in an undisturbed sleep state. this is accomplished by controlling the signal voltages such that all nodes must wake?up when they receive a higher voltage message signal waveform. the communication system communicates to the nodes information as to which nodes are to stay operational (awake) and which nodes are to put themselves into a non communicating low power asleepo state. communication at the lower, normal voltage levels shall not disturb the sleeping nodes. normal mode transmission bit rate in normal communication is 33 kbits/s. in normal transmission mode the ncv7356 supports controlled waveform rise and overshoot times. waveform trailing edge control is required to assure that high frequency components are minimized at the beginning of the downward voltage slope. the remaining fall time occurs after the bus is inactive with drivers off and is determined by the rc time constant of the total bus load. rxd output pin logic data as sensed on the single wire can bus. rxd polarity ? rxd = logic 1 on this pin indicates a bus recessive state (low bus voltage) ? rxd = logic 0 on this pin indicates a bus normal or high voltage bus dominant state rxd in sleep mode rxd does not pass signals to the microprocessor while in sleep mode until a valid wake?up bus voltage level is received or the mode0 and mode 1 pins are not 0, 0 respectively. when the valid wake?up bus voltage signal awakens the transceiver, the rxd pin signals an interrupt (logic 0). if there is no mode change within 250 ms (typ), the transceiver re?enters the sleep mode. when not in sleep mode all valid bus signals will be sent out on the rxd pin. rxd will be placed in the undriven or off state when in sleep mode. rxd typical load resistance: 2.7 k capacitance: < 25 pf
ncv7356 http://onsemi.com 12 bus load pin resistor ground connection with internal open?on?loss? of?ground protection when the ecu experiences a loss of ground condition, this pin is switched to a high impedance state. the ground connection through this pin is not interrupted in any transceiver operating mode including the sleep mode. the ground connection only is interrupted when there is a valid loss of ground condition. this pin provides the bus load resistor with a path to ground which contributes less than 0.1 v to the bus offset voltage when sinking the maximum current through one unit load resistor. the transceiver's maximum bus leakage current contribution to v ol from the load pin when in a loss of ground state is 50 a over all operating temperatures and 3.5 < v bat < 27 v. v bat input pin vehicle battery voltage the transceiver is fully operational as described in the electrical characteristics table over the range 6.0 v < v bat < 18 v as measured between the gnd pin and the v bat pin. for 5.0 v < v bat < 6.0 v, the bus operates in normal mode with reduced dominant output voltage and reduced receiver input voltage. high voltage wakeup is not possible (dominant output voltage is the same as in normal or high?speed mode). the transceiver operates in normal mode when 18 v < v bat < 27 v at 85 c for one minute. for 0 < v bat < 4.0 v, the bus is passive (not driven dominant) and rxd is undriven (high), regardless of the state of the txd pin (undervoltage lockout). can bus input/output pin wave shaping in normal and high voltage wake?up mode wave shaping is incorporated into the transmitter to minimize emi radiated emissions. an important contributor to emissions is the rise and fall times during output transitions at the acornerso of the voltage waveform. the resultant waveform is one half of a sin wave of frequency 50?65 khz at the rising waveform edge and one quarter of this sin wave at falling or trailing edge. wave shaping in high?speed mode wave shaping control of the rising and falling waveform edges are disabled during high?speed mode. emi emissions requirements are waived during this mode. the waveform rise time in this mode is less than 1.0 s. short circuits if the can bus pin is shorted to ground for any duration of time, the current is limited as specified in the electrical characteristics table until an overtemperature shutdown circuit disables the output high side drive source transistor preventing damage to the ic. loss of ground in case of a valid loss of ground condition, the load pin is switched into high impedance state. the canh transmission is continued until the undervoltage lock out voltage threshold is detected. loss of battery in case of loss of battery (v bat = 0 or open) the transceiver does not disturb bus communication. the maximum reverse current into the power supply system (v bat ) doesn't exceed 500 a. inh pin (14 pin package only) the inh pin is a high?voltage highside switch used to control the ecu's regulated microcontroller power supply. after power?on, the transceiver automatically enters an intermediate standby mode, the inh output will go high (up to v bat ) turning on the external voltage regulator. the external regulator provides power to the ecu. if there is no mode change within 250 ms (typ), the transceiver re?enters the sleep mode and the inh output goes to logic 0 (floating). when the transceiver has detected a valid wake?up condition (bus hvwu traffic which exceeds the wake?up filter time delay) the inh output will become high (up to v bat ) again and the same procedure starts as described after power?on. in case of a mode change into any active mode, the sleep timer is stopped and inh stays high (up to v bat ). if the transceiver enters the sleep mode, inh goes to logic 0 (floating) after 250 ms (typ) when no wake?up signal is present.
ncv7356 http://onsemi.com 13 figure 6. state diagram, 8 pin package hvwu mode mode1 high v bat on mode0 low high?speed mode mode1 low mode0 high normal mode mode1 high mode0 high sleep mode can float (1) low after hvwu, high after v bat on & v ccecu present wake?up request from bus after 250 ms ?> no mode change ?> no valid wake?up mode0/1 => high (if v cc_ecu on) mode0&1 => low mode0/1 => high v bat standby rxd high/low (1) mode0/1 low can float mode0/1 low
ncv7356 http://onsemi.com 14 figure 7. state diagram, 14 pin package hvwu mode mode1 high v bat on inh v bat mode0 low high?speed mode mode1 low inh v bat mode0 high normal mode mode1 high inh v bat mode0 high sleep mode inh/can floating mode0/1 low (1) low after hvwu, high after v bat on & v ccecu present wake?up request from bus after 250 ms ?> no mode change ?> no valid wake?up mode0/1 => high (if v cc_ecu on) mode0&1 => low mode0/1 => high v bat standby inh v s rxd high/low (1) mode0/1 low can float
ncv7356 http://onsemi.com 15 figure 8. application circuitry, 8 pin package ncv7356 v bat * can controller 2.7 k 5 4 rxd 2 mode0 3 mode1 1 txd 7 6 load canh 6.49 k v bat_ecu 100 pf v bat 8 gnd 100 pf 47 h esd protection ? mmbz27vclt1 ecu connector to single wire can bus *recommended capacitance at v bat_ecu > 1.0 f (immunity to iso7637/1 test pulses) mra4004t3 1 k + + 100 nf voltage regulator +5 v v bat
ncv7356 http://onsemi.com 16 figure 9. application circuitry, 14 pin package ncv7356 v bat * voltage regulator v bat +5 v can controller 2.7 k 10 5 rxd 3 mode0 4 mode1 2 txd 12 11 load canh 6.49 k v bat_ecu 100 pf v bat 1, 7, 8, 14 copper foil heatsink >150 mm 2 gnd 100 pf 47 h esd protection ? mmbz27vclt1 ecu connector to single wire can bus *recommended capacitance at v bat_ecu > 1.0 f (immunity to iso7637/1 test pulses) mra4004t3 9 inh 1 k + + 100 nf
ncv7356 http://onsemi.com 17 package dimensions so?8 d suffix case 751?07 issue ad seating plane 1 4 5 8 n j x 45 k notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. 6. 751?01 thru 751?06 are obsolete. new standard is 751?07. a b s d h c 0.10 (0.004) dim a min max min max inches 4.80 5.00 0.189 0.197 millimeters b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.053 0.069 d 0.33 0.51 0.013 0.020 g 1.27 bsc 0.050 bsc h 0.10 0.25 0.004 0.010 j 0.19 0.25 0.007 0.010 k 0.40 1.27 0.016 0.050 m 0 8 0 8 n 0.25 0.50 0.010 0.020 s 5.80 6.20 0.228 0.244 ?x? ?y? g m y m 0.25 (0.010) ?z? y m 0.25 (0.010) z s x s m 1.52 0.060 7.0 0.275 0.6 0.024 1.270 0.050 4.0 0.155 mm inches scale 6:1 recommended footprint
ncv7356 http://onsemi.com 18 package dimensions soic?14 d suffix case 751a?03 issue g notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. ?a? ?b? g p 7 pl 14 8 7 1 m 0.25 (0.010) b m s b m 0.25 (0.010) a s t ?t? f r x 45 seating plane d 14 pl k c j m dim min max min max inches millimeters a 8.55 8.75 0.337 0.344 b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.054 0.068 d 0.35 0.49 0.014 0.019 f 0.40 1.25 0.016 0.049 g 1.27 bsc 0.050 bsc j 0.19 0.25 0.008 0.009 k 0.10 0.25 0.004 0.009 m 0 7 0 7 p 5.80 6.20 0.228 0.244 r 0.25 0.50 0.010 0.019 on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, in cluding without limitation special, consequential or incidental damages. atypicalo parameters which may be provided in scillc data sheets and/or specifications can and do vary in different a pplications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical e xperts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc prod uct could create a situation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indem nify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney f ees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was neglig ent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800?282?9855 toll free usa/canada japan : on semiconductor, japan customer focus center 2?9?1 kamimeguro, meguro?ku, tokyo, japan 153?0051 phone : 81?3?5773?3850 ncv7356/d literature fulfillment : literature distribution center for on semiconductor p.o. box 61312, phoenix, arizona 85082?1312 usa phone : 480?829?7710 or 800?344?3860 toll free usa/canada fax : 480?829?7709 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : http://onsemi.com order literature : http://www.onsemi.com/litorder for additional information, please contact your local sales representative.

▲Up To Search▲

Price & Availability of NCV7356D1

	To Download NCV7356D1 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .